Method of fabricating a flash memory

ABSTRACT

A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are formed over the active region. A portion of each device isolation structure is removed to form a plurality of trenches. A dielectric layer is formed over the substrate and a sacrificial layer is filled the trenches. A portion of the dielectric layer is removed using the sacrificial layer as a self-aligned mask. The patterned mask layer is removed and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer and a control gate are formed over the substrate. A source region and a drain region are formed in the substrate on each side of the control gate.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Taiwan applicationserial no. 93103004, filed Feb. 10, 2004.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a memorydevice. More particularly, the present invention relates to a method offabricating a flash memory and floating gate.

2. Description of Related Art

Flash memory is a type of electrically erasable programmable read-onlymemory (EEPROM). Flash memory is a memory device that allows multipledata writing, reading and erasing operations. The stored data will beretained even after power to the device is removed. With theseadvantages, it has been broadly applied in personal computer andelectronic equipment. In addition, the flash memory is also a type ofhigh-speed non-volatile memory (NVM) that occupies very little space andconsumes very little power. Moreover, erasing is carried out in ablock-by-block fashion so that the operating speed is higher than mostconventional memory devices.

A typical flash memory device has a floating gate and a control gateformed by doped polysilicon. The control gate is set up directly abovethe floating gate with an inter-gate dielectric layer separating thetwo. Furthermore, a tunneling oxide layer is also set between thefloating gate and the underlying substrate (the so-called stacked gateflash memory). To operate the flash memory, a positive or negativevoltage is applied to the control gate so that electric charges can beinjected into or released from the floating gate resulting in thestorage or erasure of data.

FIGS. 1A through 1C are schematic cross-sectional views showing some ofthe steps for fabricating a conventional flash memory device. First, asshown in FIG. 1A, a substrate 100 having a plurality of device isolationstructures 102 thereon for defining active regions 104 and a tunnelingdielectric layer on the active regions 104 is provided. A conductivelayer 108 is formed over the substrate 100 to cover the device isolationstructures 102 and the tunneling dielectric layer 106. Thereafter, aplanarization operation is carried out to remove a portion of theconductive layer 108 and smooth out the top surface of the conductivelayer 108.

As shown in FIG. 1B, a patterned photoresist layer 109 is formed overthe conductive layer 108. The patterned photoresist layer 109 exposes aportion of the conductive layer 108 on the device isolation structure102. Thereafter, using the patterned photoresist layer 109 as a mask, aportion of the conductive layer 108 is removed to form a plurality oftrenches 107 in the conductive layer 108 above the device isolationstructures 102. The conductive layer 108 retained after forming thetrenches 107 becomes the floating gate 110.

After removing the patterned photoresist layer 109, an inter-gatedielectric layer 112 is formed over the substrate 100 to cover thefloating gate 110 as shown in FIG. 1C. Finally, a control gate 114 isformed over the inter-gate dielectric layer 112.

In the aforementioned fabrication process, the floating gate 110 isformed using photolithographic and etching processes. However,photolithographic and etching processes involve steps such asde-moisturize heating, coating, photoresist deposition, soft baking,photo-exposure, post photo-exposure baking, chemical development, hardbaking and etching. Hence, the process not only is time consuming butalso incurs additional production cost.

In addition, the aforementioned process utilizes a chemical-mechanicalpolishing (CMP) operation to planarize the conductive layer 108. Withouta reference polishing stop layer, the thickness of conductive layer 108retained after each chemical-mechanical polishing operation will bedifferent. In other words, there is no control over to the thickness ofthe floating gate 110.

On the other hand, a larger gate-coupling ratio (GCR) between thefloating gate and the control gate requires a lower operating voltage.The methods of increasing the gate-coupling ratio include increasing thecapacitance of the inter-gate dielectric layer or reducing thecapacitance of the tunneling oxide layer. One method of increasing thecapacitance of the inter-gate dielectric layer is to enlarge theincluded area between the control gate and the floating gate. Thus,minimizing the size of the trenches 107 is able to increase the includedarea between the floating gate and the control gate and thus increasethe gate-coupling ratio between them. However, when the conductive layer108 is patterned, size of the trenches 107 is constrained by thephotolithographic and etching processes. In other words, it is difficultto decrease the size of each trench 107 further. In the absence of anyother method for increasing the included area between the control gateand the floating gate, improving the performance of the memory device isdifficult.

SUMMARY OF INVENTION

Accordingly, the present invention is directed to a method offabricating a flash memory capable of controlling the thickness of afloating gate inside the flash memory and increasing the gate-couplingratio between the floating gate and a control gate for a higher deviceperformance.

The present invention is also directed to a method of fabricating afloating gate such that there is no need to fabricate the mask forforming the floating gate. In other words, one photolithographic andetching process can be effectively avoided so that the fabricatingprocess is more simplified.

According to an embodiment of the present invention, a method offabricating a flash memory is provided. First, a substrate with atunneling dielectric layer, a first conductive layer, a pad oxide layerand a patterned mask layer sequentially formed thereon is provided.Thereafter, using the patterned mask layer as a mask, a portion of thepad oxide layer, the first conductive layer, the tunneling dielectriclayer and the substrate are removed to form a plurality of firsttrenches in the substrate. Insulating material is deposited into thefirst trenches to form a plurality of device isolation structures. Aportion of each device isolation structure is removed to form aplurality of second trenches such that the top section of each retaineddevice isolation structure lies between the tunneling dielectric layerand the patterned mask layer. A dielectric layer is formed over thesubstrate to cover the patterned mask layer and the surface of thesecond trenches. Material is deposited into various second trenches toform a sacrificial layer. The sacrificial layer and the dielectric layerare formed by different materials each having a different etchingselectivity. Using the sacrificial layer as a self-aligned mask, aportion of the dielectric layer is removed. The patterned mask layer isremoved to expose the pad oxide layer and then the pad oxide layer isremoved to expose the first conductive layer. Thereafter, a secondconductive layer is formed over the substrate. A portion of the secondconductive layer is removed to expose the top section of the sacrificiallayer. The second conductive layer and the first conductive layertogether constitute a floating gate. The method of removing a portion ofthe second conductive layer to expose the top section of the sacrificiallayer includes performing a chemical-mechanical polishing operation.Furthermore, the second conductive layer and the sacrificial layer areformed by different materials each having a different etchingselectivity. Thereafter, the sacrificial layer is removed. An inter-gatedielectric layer is formed over the substrate to cover the floatinggate. A control gate is formed over the inter-gate dielectric layer.Finally, a source region and a drain region are formed in the substrateon each side of the control gate.

In the process of forming the floating gate, the second trenches areformed over the device isolation structures before sequentiallydepositing the dielectric material and sacrificial material into thesecond trenches to form a stack structure. Thereafter, the stackstructure is used to fabricate the floating gate. Hence, the presentinvention eliminates a mask for fabricating the floating gate. In otherwords, one photolithographic and etching process can be effectivelyavoided and hence the overall fabrication cost can be reduced.

Because the thickness of the floating gate correspond to the totalheight of the dielectric layer and the sacrificial layer, the thicknessof the floating gate is determined by the total height of the dielectriclayer and the sacrificial layer. Thus, the thickness of the floatinggate can be precisely controlled.

In addition, the size of the second trenches can be reduced by forming athicker dielectric layer. Hence, a floating gate with a larger size canbe produced. With a larger floating gate, the included area between thecontrol gate and the floating gate is increased so that a highergate-coupling ratio is obtained.

The present invention also provides an alternative method of fabricatinga flash memory. First, a substrate with a plurality of device isolationstructures for defining active regions and a tunneling dielectric layerand a patterned mask layer sequentially formed over the substrate withinthe active regions is provided. Thereafter, a portion of each deviceisolation structure is removed to form a plurality of trenches. The topsection of each retained device isolation structure lies between thetunneling dielectric layer and the patterned mask layer. A dielectriclayer is formed over the substrate to cover the patterned mask layer andthe surface of the trenches. Sacrificial material is deposited into thetrenches to form a sacrificial layer. The sacrificial layer and thedielectric layer are formed by different materials each having adifferent etching selectivity. Using the sacrificial layer as aself-aligned mask, a portion of the dielectric layer is removed.Thereafter, the patterned mask layer is removed to expose the tunnelingdielectric layer. A conductive layer is formed over the substrate.Afterwards, a portion of the conductive layer is removed to expose thetop section of the sacrificial layer. The method of removing a portionof the conductive layer to expose the top section of the sacrificiallayer includes performing a chemical-mechanical polishing operation.Furthermore, the conductive layer and the sacrificial layer are formedby different materials each having a different etching selectivity.Finally, the sacrificial layer is removed.

In the process of forming the floating gate, the trenches are formedover the device isolation structures before sequentially depositing thedielectric material and sacrificial material into the trenches to form astack structure. Thereafter, the stack structure is used to fabricatethe floating gate. Hence, the present invention eliminates the need tofabricate a mask for fabricating the floating gate. In other words, onephotolithographic and etching process can be effectively avoided andhence the overall fabrication cost can be reduced.

Because the thickness of the floating gate correspond to the totalheight of the dielectric layer and the sacrificial layer, the thicknessof the floating gate is determined by the total height of the dielectriclayer and the sacrificial layer. Thus, the thickness of the floatinggate can be precisely controlled.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIGS. 1A through 1C are schematic cross-sectional views showing some ofthe steps of fabricating a conventional flash memory device.

FIGS. 2A through 2F are schematic cross-sectional views showing thesteps of fabricating a flash memory according to one embodiment of thepresent invention.

DETAILED DESCRIPTION

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIGS. 2A through 2F are schematic cross-sectional views showing thesteps for fabricating a flash memory according to one embodiment of thepresent invention. As shown in FIG. 2A, a substrate 200 such as asilicon substrate is provided. Thereafter, a tunneling dielectric layer206, a conductive layer 208, a pad oxide layer 209 and a patterned masklayer 210 are sequentially formed over the substrate 200. The patternedmask layer 210 has openings 202 that expose areas for forming a deviceisolation structure.

The tunneling dielectric layer 206 is silicon oxide layer having athickness between about 70 Å to 90 Å formed, for example, by performinga thermal oxidation process. The conductive layer 208 is a dopedpolysilicon layer formed, for example, by performing a chemical vapordeposition process to form an undoped polysilicon layer (not shown) andthen implanting ions into the undoped layer to form a doped polysiliconlayer having a thickness between about 500 Å to 1000 Å. The pad oxidelayer 209 is a silicon oxide layer having a thickness between about 15 Åto 50 Å formed, for example, by performing a thermal oxidation process.Furthermore, the patterned mask layer 210 is formed by a material havingan etching selectivity that differs from the pad oxide layer 209, theconductive layer 208, the tunneling dielectric layer 206 and thesubstrate 200. The patterned mask layer 210 is a silicon nitride layerhaving a thickness between about 1500 Å to 2000 Å, for example. Thepatterned mask layer 210 is formed, for example, by performingphotolithographic and etching processes.

As shown in FIG. 2B, a portion of the pad oxide layer 209, theconductive layer 208, the tunneling dielectric layer 206 are removedusing the patterned mask layer 210 as an etching mask to form aplurality of trenches 212. Ultimately, a tunneling dielectric layer 206a, a conductive layer 208 a and a pad oxide layer 209 a remain on top ofthe substrate 200. The trenches 212 have a depth of, for example,between about 3000 Å to 4000 Å.

Thereafter, an insulating material is deposited into the trenches 212 toform a plurality of device isolation structure 214 for defining anactive region 204. The device isolation structure 214 is formed, forexample, by performing a high-density plasma chemical vapor deposition(HDP-CVD) process to form a layer of insulation material (not shown) andthen performing a chemical-mechanical polishing (CMP) operation toremove material outside the trenches.

It should be noted that, in this embodiment, the tunneling dielectriclayer 206 is formed before forming the device isolation structures 214.This can prevent the formation of bird's beak in the neighborhood of thedevice isolation structure due to a subsequent thermal process if thedevice isolation structure 214 is formed first.

As shown in FIG. 2C, a portion of the insulation material in each deviceisolation structures 214 is removed to form a plurality of trenches 215.A top section of the remaining device isolation structure 214 a liesbetween the tunneling dielectric layer 206 a and the patterned masklayer 210. The method of removing a portion of the insulation materialfrom the device isolation structures 214 to form the trenches 215includes a dry etching process.

Thereafter, a dielectric layer 216 is formed over the substrate 200 tocover the patterned mask layer 210 and the surface of the trenches 215.The dielectric layer 216 is formed by a material having an etchingselectivity that differs from the material for forming a conductivelayer in a subsequent process. The dielectric layer 216 is a siliconnitride layer having a thickness between about 200 Å to 1000 Å formed,for example, by performing a chemical vapor deposition process. In thisembodiment, both the dielectric layer 216 and the patterned mask layer210 are formed by an identical material.

Sacrificial material is deposited into each trench 215 to form asacrificial layer 218. The sacrificial layer 218 is formed by a materialhaving an etching selectivity that differs from the material for forminga conductive layer in a subsequent process. The sacrificial layer 218 isa silicon oxide layer formed, for example, by depositing a layer ofsacrificial material (not shown) and then performing achemical-mechanical polishing operation or a back-etching process toremove sacrificial material lying outside the trenches 215. In anotherpreferred embodiment, the sacrificial layers 218 are formed, forexample, by spin-coating a layer of spin-on glass (SOG) over thesubstrate 200 to form a sacrificial layer (not shown) and then etchingback the excess sacrificial material outside the trenches 215.

As shown in FIG. 2D, using the sacrificial layers 218 as a self-alignedmask, a portion of the dielectric layer 216 is removed. Since thesacrificial layers 218 and the dielectric layer 216 are fabricated frommaterials having a different etching selectivity, most of the dielectriclayer 216 is removed except the dielectric layer 216 a underneath thesacrificial layers 218. The dielectric layer 216 a and the sacrificiallayer 218 together form a sacrificial stacked layer 217. Because thedielectric layer 216 and the patterned mask layer 210 are formed by thesame material (for example, silicon nitride) in this embodiment, theprocess of removing a portion of the dielectric layer 216 also removesthe patterned mask layer 210.

Thereafter, the pad oxide layer 209 a is removed to expose theconductive layer 208 a. The pad oxide layer 209 a is removed, forexample, by wet etching using hydrofluoric acid solution as the etchant.A conductive layer 220 is formed over the substrate 200. With theconductive layer 208 a already formed underneath, the conductive layer220 is easier to form on top. In addition, the conductive layer 220 isformed by doped polysilicon, for example. The doped polysilicon layer isformed, for example, by performing a chemical vapor deposition processto form an undoped polysilicon layer (not shown) and then implantingions into the undoped polysilicon layer.

As shown in FIG. 2E, a portion of the conductive layer 220 is removed toexpose the top section of the sacrificial layer 218 so that the retainedconductive layer 220 a and the conductive layer 208 a togetherconstitute a floating gate 221. The method of removing a portion of theconductive layer 220 to expose the top section of the sacrificial layer218 includes performing a chemical-mechanical polishing operation usingthe sacrificial layer 218 as a polishing stop layer. Hence, the retainedconductive layer 220 a has a thickness related to the total height ofthe sacrificial stacked layer 217. In other words, a better control ofthe thickness of the floating gate 221 is obtained.

It should be noted that the thickness of the dielectric layer 216 on thesidewalls of the trenches 215 in FIG. 2C directly affects the size ofthe conductive layer 220 a. That is, it also affects the overlappingarea between the floating gate 221 and the control gate (not shown).Consequently, in the aforementioned step, a thicker dielectric layer 216can be used to reduce the width of the trench 215 so that the distancebetween neighboring conductive layers 220 a can be reduced. For example,in FIG. 2C, if the original width W1 of the trench 215 is 2000 Å and thewidth W2 of the patterned mask layer 210 between two trenches 215 is1500 Å, the width W3 of the trench 215 would be 1000 Å after depositinga dielectric layer 216 with a thickness of about 500 Å. Hence, theconductive layer 220 a originally having a maximum width of about 1500 Å(width W2 of the patterned mask layer 210) can have a wider width W4 ofabout 2500 Å as shown in FIG. 2E. In other words, electrical performanceof the memory device can be increased by forming a thicker dielectriclayer 216 to increase the overlapping area between the floating gate 221and the control gate.

As shown in FIG. 2F, the sacrificial layers 218 are removed. Thesacrificial layers 218 are removed, for example, by wet etching usinghydrofluoric acid solution as the etchant. It should be noted that, inthis embodiment, the trenches 215 are formed before the sacrificialstacked layer 217 that includes the dielectric layer 216 and thesacrificial layer 218 being formed. Then, the floating gate 221 isformed utilizing the sacrificial stacked layer 217 as the etching stoplayer. Consequently, one photolithographic process is omitted and theproduction cost is reduced.

Thereafter, an inter-gate dielectric layer 222 is formed over thesubstrate 200 to cover the dielectric layer 216 a and the floating gate221. The inter-gate dielectric layer 222 is an oxide/nitride/oxidecomposite layer, for example. The inter-gate dielectric layer 222 isformed, for example, by performing a thermal oxidation process to form asilicon oxide layer over the substrate 200 and then performing achemical vapor deposition process to form a silicon nitride layer andanother silicon oxide layer over the first silicon oxide layer. Theoxide/nitride/oxide composite layer has a first oxide layer with athickness between 40 Å to 50 Å, a silicon nitride layer with a thicknessbetween 45 Å to 70 Å and a second silicon oxide between 50 Å to 70 Å.Obviously, the inter-gate dielectric layer 222 can be an oxide/nitridecomposite layer too.

A control gate 224 is formed over the inter-gate dielectric layer 222.The control gate 224 is a doped polysilicon formed, for example byperforming a chemical vapor deposition process to form a layer ofundoped polysilicon (not shown) and implanting ions into the undopedpolysilicon layer. Thereafter, a source region (not shown) and a drainregion (not shown) are formed in the substrate on each side of thecontrol gate 224. The source region and the drain region are formed, forexample, by implanting impurities into the substrate 200 on each side ofthe control gate 224. Since subsequent fabrication processes should befamiliar to those skilled in the techniques, detailed description isomitted here.

Aside from the aforementioned embodiment of the present invention, itshould be noted that there is another embodiment. After removing the padoxide layer 208 a in FIG. 2D, the conductive layer 208 a is removedbefore carrying out the step for forming the conductive layer 220 andthe processes as shown in FIGS. 2E and 2F. Hence, the completed flashmemory has a floating agate 221 including just the conductive layer 220a. Furthermore, in another preferred embodiment, a substrate 200 withonly a tunneling dielectric layer 206 and a patterned mask layer 210thereon is provided in FIG. 2A. Thus, the floating gate 221 of the flashmemory also includes a single conductive layer 220 a only. In yetanother preferred embodiment, after removing the sacrificial layers 218in FIG. 2F, further includes removing the dielectric layer 216 a beforecarrying out the steps for forming the inter-gate dielectric layer 222and the control gate 224.

In summary, major advantages of the present invention includes:

1. Trenches are formed over the device isolation structures beforedepositing dielectric material and sacrificial material into them toform a stack structure. Thereafter, the stack structure is used tofabricate the floating gate. Hence, the present invention eliminates theneed to fabricate a mask for fabricating the floating gate. In otherwords, one photolithographic and etching process can be effectivelyavoided and hence the overall fabrication cost can be reduced.

2. Because the thickness of the floating gate correspond to the totalheight of the dielectric layer and the sacrificial layer, the thicknessof the floating gate is determined by the total height of the dielectriclayer and the sacrificial layer. Thus, the thickness of the floatinggate can be precisely controlled.

3. With the size of the second trenches reduced by forming a thickerdielectric layer, a floating gate with a larger size can be produced.With a larger floating gate, the included area between the control gateand the floating gate is increased so that a higher gate-coupling ratioand hence a better electrical performance of the device is obtained.

4. The tunneling dielectric layer is formed before carrying out varioussteps for fabricating the device isolation structures. This can preventthe formation of bird's beak in the neighborhood of the device isolationstructure due to a subsequent thermal process when the device isolationstructure is formed first. Ultimately, the electrical performance of thememory device is improved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A method of fabricating a flash memory, comprising the steps of:providing a substrate having a tunneling dielectric layer, a firstconductive layer, a pad oxide layer and a patterned mask layer formedthereon; removing portions of the pad oxide layer, the first conductivelayer, the tunneling dielectric layer and the substrate using thepatterned mask layer as an etching mask to form a plurality of firsttrenches in the substrate; depositing an insulating material into thefirst trenches to form a plurality of device isolation structures;removing a portion of each device isolation structure to form aplurality of second trenches such that the top section of each retaineddevice isolation structure lies between the tunneling dielectric layerand the patterned mask layer; forming a dielectric layer over thesubstrate to cover the patterned mask layer and the surface of thesecond trenches; filling the second trenches with sacrificial materialso as to form sacrificial layers; removing a portion of the dielectriclayer using the sacrificial layers as self-aligned masks; removing thepatterned mask layer to expose the pad oxide layer; removing the padoxide layer to expose the first conductive layer; forming a secondconductive layer over the substrate; removing a portion of the secondconductive layer to expose a top section of the sacrificial layers,wherein the second conductive layer and the first conductive layertogether form a plurality of floating gates; removing the sacrificiallayer; forming an inter-gate dielectric layer over the substrate tocover the floating gate; forming a third conductive layer over theinter-gate dielectric layer to form a plurality of control gates; andforming a plurality of source/drain regions in the substrate on eachside of the control gates.
 2. The method of claim 1, wherein a materialof the sacrificial layer and the dielectric layer have different etchingselectivity and a material of the sacrificial layer and that of thesecond conductive layer have different etching selectivities.
 3. Themethod of claim 2, wherein the material of the sacrificial layercomprises silicon oxide.
 4. The method of claim 2, wherein the materialof the dielectric layer comprises silicon nitride.
 5. The method ofclaim 1, wherein the step for removing a portion of the secondconductive layer to expose the top section of the sacrificial layercomprises performing a chemical-mechanical polishing operation.
 6. Themethod of claim 1, wherein the dielectric layer and the patterned masklayer are formed by identical material so that the patterned mask layeris also removed in the process of removing a portion of the dielectriclayer.
 7. The method of claim 1, further comprising a step of removingthe dielectric layer after the step of removing the sacrificial layerbut before the step of forming the inter-gate dielectric layer.
 8. Themethod of claim 1, wherein the step of forming the second trenchescomprises etching back in a dry etching operation.
 9. The method ofclaim 1, further comprising a step of totally removing the firstconductive layer after the step of removing the pad oxide layer butbefore the step of forming the second conductive layer.
 10. A method offabricating a floating gate, comprising the steps of: providing asubstrate having a plurality of device isolation structures for definingan active region and a tunneling oxide layer and a patterned mask layersequentially formed within the active region over the substrate;removing a portion of each device isolation structure to form aplurality of trenches, wherein the top section of each retained deviceisolation structure is disposed between the tunneling dielectric layerand the patterned mask layer; forming a dielectric layer over thesubstrate to cover the patterned mask layer and the surface of thetrenches; filling the trenches with sacrificial material so as to formsacrificial layers; removing a portion of the dielectric layer using thesacrificial layers as a self-aligned mask; removing the patterned masklayer to expose the tunneling dielectric layer; forming a firstconductive layer over the substrate; removing a portion of the firstconductive layer to expose the top section of the sacrificial layers;and removing the sacrificial layers.
 11. The method of claim 10, whereina material of the sacrificial layer and the dielectric layer havedifferent etching selectivities and a material of the sacrificial layerand the first conductive layer have different etching selectivities. 12.The method of claim 11, wherein the material of the sacrificial layercomprises silicon oxide.
 13. The method of claim 11, wherein thematerial of the dielectric layer comprises silicon nitride.
 14. Themethod of claim 10, wherein the step for removing a portion of the firstconductive layer to expose the top section of the sacrificial layercomprises performing a chemical-mechanical polishing operation.
 15. Themethod of claim 10, wherein the dielectric layer and the patterned masklayer are formed by identical material so that the patterned mask layeris also removed in the process of removing a portion of the dielectriclayer.
 16. The method of claim 15, wherein a material of the dielectriclayer and the patterned mask layer comprises silicon nitride.
 17. Themethod of claim 10, wherein the step of forming the trenches comprisesetching back in a dry etching operation.
 18. The method of claim 10,further comprising a step of removing the dielectric layer after thestep of removing the sacrificial layers.
 19. The method of claim 10,wherein a second conductive layer and a pad oxide layer are formedbetween the tunneling oxide layer and the patterned mask layer, and themethod further comprises a step of removing the pad oxide layer afterthe step of removing the mask layer.
 20. The method of claim 19, furthercomprising a step of removing the second conductive layer after the stepof removing the pad oxide layer.